Bypass capacitors routing

Community PCB Design
1

I’m using an FT256 BGA part with 1mm pitch (an FPGA). This is a 4-layer board: 2 signal, power and ground planes.

I’m placing a bypass caps for each power pin close to the FPGA on both signal layers.

The question is how exactly do I route the power pins of the bypass capacitors. Is it just a via to the power plane or a dedicated route to the corresponding power pin of the chip (which has a via to the power plane)

Thanks

2

Use vias to the ground and power planes. Have them as close to the capacitor as possible, with wide tracks, to minimise inductance

Look for the high-speed PCB design app notes on the Xilinx web site, they are very good.

Leon

3

Leon,

I disagree. If you don’t use dedicated traces from the caps to the IC power pins, you are basically just adding extra capacitance t the board overall. If you were wire wrapping or point to point soldering a board and needed to add a bypass cap to a part, would you wire it directly between the power pins or just attach it to some of the nearby power leads? Of course, you’d wire it directly between the pins. The same is true with PCBs. If the bypass cap doesn’t have dedicated leads connecting it across power pins, then how is the capacitor supposed to suppress the noise at that chip?

Thanks,

PeterM

4

I’m referring to high-speed designs with multi-layer boards, which is what the OP is using. The vias are even placed in the pads, or two vias are used for each pad, sometimes, to reduce inductance still further. See the Xilinx app notes, as I suggested.