This is my first board design, and I’d appreciate it if someone would look it over quickly and see if I’ve made any really obvious mistakes. The board uses an AT32UC3B256, the ENC28J60 Ethernet interface, and a MagJack. I combined the Copper board from StackFoundry, and the example schematic for the Ethernet interface board (BOB-00765) on sparkfun.
You REALLY need to try to include a groundplane, especially since you’ve got some high-speed signals there. I suggest you try to dedicate as much of the bottom layer as possible to a groundplane.
I realize that a complete groundplane won’t be possible, but you could make big improvements on what you have now. Move components around if you need to.
I’d have used a four-layer board for that.
I agree that a 4 layer board would be best, but think it would be possible to do OK with 2 layers. Costs are much higher for 4-layer prototype boards - not always an option for hobbyists.
The board image is too small for me to see properly, but it looks like you just hit autoroute and called it a day. The routing is really messy.
Thank you for your responses. As the board is small, a four layer board wouldn’t be too much of a problem. However, the free-ware version of eagle only supports layers, and the commercial version is too expensive for this project. I was wondering if I needed a ground plane, but I didn’t know if it was required. Does anyone have any good references on ground plane design? If I do a four layer board, do I just dedicate a layer to ground, and fill it will a polygon?
A few of the traces were auto-routed, but most were done manually.
If you do use a 4-layer board, dedicate a layer for GND, and a layer for 3.3V. Normally these will be the inner layers.
I still think it would be possible to do a reasonable job of this with a 2-layer board, but it will take a fair bit of rework. I’d delete all of the tracks, then re-arrange the parts to minimize the tracks. Then re-route by hand, trying to get all tracks on the top layer. This won’t be possible, but minimize the amount and length of tracks you have on the bottom layer. Make sure that the high-speed data lines have an unbroken groundplane under them.
IMHO, you might want to follow some basic guidelines like making top layer tracks as much horizontal direction possible and the other layer as much vertical as possible. By doing this, your plane will be less being “sliced” by the tracks. I think 2 layer is adequate unless you are going for some certification. The board can also be smaller I guess. 
A couple of quick schematic notes:
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The RGB status LED doesn’t have any netnames on the far side of the current limiting resistors
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You are missing a connection dot on the reset pullup resistor
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The magjack isn’t hooked up to the ENC28j60
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You seem to have very little bulk capacitance on the 5V rail. Check U2’s requirements for both input and output capacitors.
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Stylistic note: You are mixing units - you have both 0.1uF and 100nF caps; these will show up as different parts in the BOM
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Stylistic note: Don’t have 4-way connections in a schematic - it’s to easy to accidentally miss shorts that way
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Stylistic note: Usually reference designators don’t include functionality - all resistors would be R1, R2, … Rn etc.
It’s hard to make out much on the board, however:
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Power and ground traces are way to thin (the main issue here is inductance rather than DC current handling capacity
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Decoupling caps shouldn’t be bunched like that. One should be next to every power pin.
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Traces should bend at 45 degree angles, not 90 degree angles
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The ground for the crystal caps should return to the ground pin on the processor via a separate trace.
/mike
Thank you for taking the time to look it over. I’m currently redesigning the board.
n1ist:
- The magjack isn’t hooked up to the ENC28j60
It is connected. however, I did not label the nets properly.
n1ist:
- You seem to have very little bulk capacitance on the 5V rail. Check U2’s requirements for both input and output capacitors.
It’s probably not enough. I was wondering about that.
n1ist:
- Stylistic note: Don’t have 4-way connections in a schematic - it’s to easy to accidentally miss shorts that way
What do you mean by this? I can’t find the part on the schematic you are referring to.
n1ist:
- Stylistic note: Usually reference designators don’t include functionality - all resistors would be R1, R2, … Rn etc.
I was doing this so it would be easier to know what a component did when I was laying the board out.
n1ist:
It’s hard to make out much on the board, however:
Once I have a reworked board, I’ll post a larger image.
n1ist:
- Power and ground traces are way to thin (the main issue here is inductance rather than DC current handling capacity
The traces are 10mil. Is there a rule for the width of power traces?
How close to the pins should they be?n1ist:
- Decoupling caps shouldn’t be bunched like that. One should be next to every power pin.
brendan0powers:
n1ist:
- Stylistic note: Don’t have 4-way connections in a schematic - it’s to easy to accidentally miss shorts that way
What do you mean by this? I can’t find the part on the schematic you are referring to.
He means this:
http://users.adam.com.au/mnoble/No_4way_junctions.JPG
As close as you can "reasonably" manage. The higher the current (ie, faster risetime of digital signals), the more important this is.brendan0powers:
How close to the pins should they be?n1ist:
- Decoupling caps shouldn’t be bunched like that. One should be next to every power pin.
I have re-worked the board. I removed all the traces, rearranged the components, and then routed the traces manually. I was not able to keep an unbroken ground plane under all the high speed traces, but I was able to minimize it. I still need to add more capacitors to the 5v net. I’m having some trouble with the width of the power and ground traces. I haven’t been able to find a good resource that explains how inductance matters with power traces.
I’ve attached a new image of the board.
You don’t want traces between pads like on pads 14-15 - it’s bad practice.
Your component designators should always be R1, R2, etc. Things like PCA, PC1, etc are confusing. I see that I’m not the first to mention this. This is a blatant mistake. It’s not even stylistic. It’s a mistake.
Your silkscreen is covering your pads, I think. I haven’t used Eagle in years so I could be mistaken. But it looks like you’re placing your designators on top of your components? Why?
What’s with PCA? a 470pf decoupling capacitor? That is pretty unusual.
I thought Ethernet was supposed to have controlled impedance or controlled length traces. I don’t remember.
220 ohm resistors on all three colors of LEDs? Different LED colors have different voltage drops - thus they’re going to be different brightnesses. Also, 220 ohms is going to make em nice and bright. Too bright IMHO.
You didn’t include a value for UL1. That should be on the schematic.
You should have a decoupling capacitor on every VDD/VCC pin.
You should ground the 4 pads that are part of the metal shell of the USB connector. Put a via on each one, or even a couple vias. This is for mechanical strength.
I don’t see a pin 1 indicator on the network IC footprint. The footprint seems to be missing its top as well. I also don’t see a part number, or a designator.
Some discretes are too close - ie NR1 and NR2, NC2 and NC3, etc.
Your board shape is not rectangular - is that intentional?
That should get you started. For a first board this looks really good, so I hope you don’t take my list as an insult.
To answer your question regarding trace inductance - I wouldn’t worry about that for this board. Worry more about just having thick enough traces. I’d aim to have no more than 10C temperature rise on your traces.
NleahciM, thanks for your reply. I have a few questions.
Why does placing a via on the USB pads add strength?
Why are NR1, NR2, NC2, etc… to close? They pass the DRC tests with files from SparkFun and Seeed Studio.
brendan0powers:
NleahciM, thanks for your reply. I have a few questions.Why does placing a via on the USB pads add strength?
Why are NR1, NR2, NC2, etc… to close? They pass the DRC tests with files from SparkFun and Seeed Studio.
Pads are just pieces of copper that have been laminated to FR-4. Their strength is pretty minimal (I was told that they’re designed to be able to hold 5 pounds/in^2). Placing a via on a pad connects it to many layers, increasing the strength of the connection by (probably) a couple orders of magnitude.
I can’t comment on the DRC tests that you ran - I can only say that the parts will be a bit tricky to solder. I say this from personal experience, not from a rule. I suspect that the tests you ran were just checking to see if the PCB is manufacturable - which those pads certainly are. I’ve never seen a hand solderability DRC check - but it’d be neat!
Can you recommend a good distance to space components? Also, I plan to re-flow solder this board.
brendan0powers:
Can you recommend a good distance to space components? Also, I plan to re-flow solder this board.
For the absolute highest density - at least maintain a sliver of soldermask between the pads. Typical, the hole in your soldermask is expanded a bit on all sides. A typical expansion is 4 mils. My PCB fab of choice does not like to manufacture soldermask that is less than 4 mils thick, so that means you want at least 12 mils from the edge of one pad to the edge of the next.
That will be pretty tight, however.
Half of the smallest discrete you’re using seems like a reasonable, though fairly aggressive, rule of thumb. So in your case, it looks like you’re using 0603s, so 15 mils. But if you don’t have steady hands or would just rather an easier to solder board - I’d go for a minimum space between pads of adjacent components of 100% of the width of your smallest discrete - so 30 mils on this board.
It really is all about how much effort you want to put into soldering this board and how skilled you are.
I have just finished a new version of the board and schematic. I think I have addressed most of the comments.
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Cleaned up the schematic, labeled all connected nets, fixed components names, and removed 4 way connections.
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The traces are wide enough to handle the current draw with less than a 10C rise in temp.
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All traces bend at 45 degree angles.
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Traces no longer go directly between two pads.
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The silkscreen does not cover the pads when I create the gerber files.
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I’ve looked at the datasheet for the CPU, and added 30 more decoupling capacitors. As well as to 0.1uF capacitors to the voltage regulator.
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The TX+/TX- and Rx+/Rx- ethernet traces are balanced to within 0.1mm.
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Added a value for UL1. I’m not sure what the value for ferrite beads is, so I added three.
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The USB pads are grounded with vias
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I fixed the footprints for the network IC and the magjack.
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Almost all components are 30mil apart. There are a couple that are 20mil apart.
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The board is now rectangular
There are two things I’m not quite sure on.
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The traces for the crystals go to the ground plane, instead of back to a ground pin on the CPU. I could not find a way to avoid this.
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I’m now powering the LED from 3.3v. The blue and green channels have a voltage of 3.5 volts. So, I didn’t add a resistor to those to channels.
For the red channel, I added a 75Ohm resistor that should result in 1.8V at 20mA. That results in a voltage 0.2V under the recommended voltage for all 3 channels.
Will this work?
I think you may have gone a little overboard on the decoupling capacitors there. Also ideally, each capacitor should have its own low inductance/impedance path to ground, ie. a via to ground for each one.