Please review my tiny led backpack pcb

Community PCB Design
1

Hi all,

This is my first PCB, it’s a backpack for an 8x8 led matrix. The matrix itself is pretty small, so this PCB is a lot smaller than I’d like :slight_smile: I used TinyCAD and FreePCB to do the schematic and pcb. I would be eternally grateful if any of you could take a look and let me know if there are any problems.

The PCB itself is tiny, ~1.2 inches square. I tried packing it all in on a 2 layer board, but I quickly realized I’d need 4 layers. I plan on having this fabbed at BatchPCB, so keep that in mind in case you see anything that they can’t do.

I’ve designed the layers as such:

top

+5

GND

bottom

FreePCB’s DRC passed with the following rules (all units are mils):

min. trace width: 8

min pad to pad: 8

min pad to trace: 8

min trace to trace: 8

min hole to pad or trace: 15

min hole to hole: 25

min annular ring (pins): 7

min annular ring (vias): 5

min board edge to any copper: 25

min copper area to copper area: 10

will these satisfy BatchPCB’s rules? I’m most concerned about clearance issues and obvious design mistakes. For example, is it a good idea to have two or more traces running parallel in different layers? Are my decoupling caps close enough? etc

And finally, the images:

Schematic:

http://i29.tinypic.com/2gvkkcg.png

Top:

http://i30.tinypic.com/2h2kqdz.png

+5:

http://i32.tinypic.com/2im4aa.png

GND:

http://i26.tinypic.com/xg0a39.png

Bottom:

http://i31.tinypic.com/34y88pu.png

All Layers:

http://i25.tinypic.com/oayzp1.png

any advice will be greatly appreciated!

2

arader:
will these satisfy BatchPCB’s rules? I’m most concerned about clearance issues and obvious design mistakes. For example, is it a good idea to have two or more traces running parallel in different layers? Are my decoupling caps close enough? etc

I can’t help you with all your questions but you should be fine for most of those DRC rules as the minimum for BatchPCB is 7mil and it looks like you have used 8mil rules.

If in doubt just submit it and see what the bot says.

3

Greetings Andy,

arader:
This is my first PCB, it’s a backpack for an 8x8 led matrix.

…

any advice will be greatly appreciated!

Looks good (especially for a first attempt). To find out

if the BatchPCB Bot can accept your design just upload it.

(There’s no obligation to order - even if it passes with

no errors).

The three issues I’ve noticed are:

(1) RST doesn’t connect to any of the SPI connectors,

so how will you program the AVR?

(2) There are no mounting holes on the PCB, how does

the PCB/Display mount?

(3) If multiple modules are connected together, how do

they know which one is being addressed? (I would have

expected links, a jumper, or other binary device to

code each module. Are you customizing the AVR code for

each one?

Also, if you had a bigger AVR (more IO) the SPI MUX

chips would go away - possibly saving some PCB

crowding?

If all modules were slaved to one master (which may be

different to the others, and indeed not require the small

footprint), wouldn’t you only need one SPI bus that drops

at each module? This would save some parts?

Have you considered breadboarding this design? A

four layer PCB is a big investment.

Comments Welcome!

4

Your +5 and GND layers appear to be non-functional, due to being split into non-connected areas by the various traces you have running on them. A 4-layer board would ideally have NO traces on the inner layers.

Shouldn’t the SPI connectors on opposite edges of the board be oriented the same way, so that adjacent modules can simply plug into each other?

5

jasonharper:
Your +5 and GND layers appear to be non-functional, due to being split into non-connected areas by the various traces you have running on them. A 4-layer board would ideally have NO traces on the inner layers.

Shouldn’t the SPI connectors on opposite edges of the board be oriented the same way, so that adjacent modules can simply plug into each other?

Yup - for example, pin 6 of J3 is floating due to this.

The layout is just in general sloppy and needs a lot of improvement. It should be pretty feasible to get most if not all of the traces out of the two power planes.

6

bigglez:
Looks good (especially for a first attempt).

Thanks!

bigglez:
(1) RST doesn’t connect to any of the SPI connectors,

so how will you program the AVR?

I didn’t want to squeeze on a 6pin connector that will only be used every once and a while, especially since I already have headers for all of the pins needed. When I program I’ll just be using a wire from the RST pin to the programmer.

bigglez:
(2) There are no mounting holes on the PCB, how does

the PCB/Display mount?

Good point. The display will just be directly mouted to the pcb via its pins, but I haven’t really thought about how I want to mount the board yet. If I can free up enough space on the corners I’ll definitely be adding mounting holes.

bigglez:
(3) If multiple modules are connected together, how do

they know which one is being addressed? (I would have

expected links, a jumper, or other binary device to

code each module. Are you customizing the AVR code for

each one?

Also, if you had a bigger AVR (more IO) the SPI MUX

chips would go away - possibly saving some PCB

crowding?

If all modules were slaved to one master (which may be

different to the others, and indeed not require the small

footprint), wouldn’t you only need one SPI bus that drops

at each module? This would save some parts?

I’m trying to create a design that uses a “decentralized” protocol, I don’t want to have a central master with many slaves. If I did use 1 SPI bus I’d need some set amount of SS lines. Depending on the number of SS lines I create in the initial design, I’d be limited to the number of devices I can add. Instead if each backpack only talks to the 4 directly connected to it, I can get something that more closely relates to the internet. By making it so that each backpack only has 4 SS lines (and thus, the SS lines aren’t shared by all nodes) the SPI bus can’t be shared, since it would be impossible for nodes not directly connected to a “talking” node to know if the bus is in use. This also means I can have many different nodes communicating at once, something that might be important down the line.

bigglez:
Have you considered breadboarding this design? A

four layer PCB is a big investment.

I do plan on bread boarding some, but after seeing the PCB it seems like it would make much more sense to do a lot of it :slight_smile: Also, other than being slightly more money, is there an difference in a 4 layer board?

jasonharper:
Your +5 and GND layers appear to be non-functional, due to being split into non-connected areas by the various traces you have running on them. A 4-layer board would ideally have NO traces on the inner layers.

Great find! so I guess my question is, with this small of an area and this many parts, is it feasible to expect no traces on the inner layers? This was my very first design, so I know it’s going to suck, but it felt like it would be very hard to keep everything on 2 layers. If people here think it’s doable, I’ll definitely shoot for it though :slight_smile:

jasonharper:
Shouldn’t the SPI connectors on opposite edges of the board be oriented the same way, so that adjacent modules can simply plug into each other?

Yes and no :slight_smile: I’ve arranged them this way so the pcb can be rotated and each side is exactly the same. I just need to make some special header that corrects the pins, and from there the pcbs can be connected in any fashion. If I went with a direct connection, the left/right and top/bottom would be different and I wouldn’t be able to mate them if the node was rotated.

So, underlying theme so far: I should try again :slight_smile: This time I’ll shoot for no traces on pwr/gnd planes. Does anyone have any advice for this? I’ve looked at a few guides and it seems like its just “start with the longest line”. How much would re-arranging the parts fix the routing issues?

thanks guys!

7

Greetings Andy,

arader:
I’m trying to create a design that uses a “decentralized” protocol, I don’t want to have a central master with many slaves. If I did use 1 SPI bus I’d need some set amount of SS lines. Depending on the number of SS lines I create in the initial design, I’d be limited to the number of devices I can add.

Why would the data flow in both directions? Doesn't

new data arrive and flow from module to module?

A time-division-Mux’d scheme would have one talker and many

listeners, each sync’d by a frame word or gap in transmission,

and each listens to all messages and only grabbing those with

the correct address block. As more modules are added the

message stream gets longer, but the basic timing is fixed.

Are you familiar with DMX-512 control for stage lighting?

This thread needs to go back to the projects forum, and

only PCB related discussion continue here, don’t you

agree?

arader:
Instead if each backpack only talks to the 4 directly connected to it, I can get something that more closely relates to the internet.

The internet?

arader:
Great find! so I guess my question is, with this small of an area and this many parts, is it feasible to expect no traces on the inner layers? This was my very first design, so I know it’s going to suck, but it felt like it would be very hard to keep everything on 2 layers. If people here think it’s doable, I’ll definitely shoot for it though :slight_smile:

Part of the problem is that you are attempting a

complex design for your first project. Also, I’m

unfamiliar with the tools you are using, but it

looks as if there is no ERC and DRC functions,

that would catch silly (and obscurely silly) errors.

arader:
So, underlying theme so far: I should try again :slight_smile: This time I’ll shoot for no traces on pwr/gnd planes. Does anyone have any advice for this? I’ve looked at a few guides and it seems like its just “start with the longest line”. How much would re-arranging the parts fix the routing issues?

In general a four layer board has two strikes compared

with a two layer board. (1) the inner layers can’t be

probed or modded, (2) The PCB house has to do

electrical testing to ensure the inner layers are correctly

manufactured. Both add to cost and complexity.

If a traditional prototype (with hand wiring) is not

your cup of tea, consider making a two sides over-size

prototype to prove the concept. Sounds as if you’d need

four (or more) modules to work out the comms?

Once you have these working together spin the PCB

layout (adding more layers) to reach the final size.

Comments Welcome!

8

Four-layer PCBs are about twice as expensive as double-sided.

It would be cheaper to go for a double-sided board by using, say, 6/6 mil design rules and 0.3 mm hole vias; you should be able to squeeze everything in. Most PCB suppliers can manage those design rules.

A four-layer board with true ground and power planes in the middle would be better in terms of EMC, but you don’t need to bother about it for a hobbyist project.

Leon

9

I’ve moved the design portion of the discussion into the project thread I have: viewtopic.php?p=50223#50223

If there are any more comments on the PCB however, please feel free!

10

Did you try to hand route the PCB, or was it done with the autorouter? I’ve found so far that I can hand route a board considerably better than (gEDA PCB) can autoroute it… so I hand route everything. Hand routing may get you two layers. It’s not a sin to use the odd link wire, either, if it can save a layer.

It’s also worth seeing if you can reduce the component count, for example, can you eliminate some of the 74 series logic by moving their jobs into a bigger AVR? According to Google, the TPIC6C595 is a shift register - could its function be done in software by an AVR instead? Using a bigger AVR to reduce the chip count by 4 would make the PCB far easier to route, and easily 2 layer. If the logic functions absolutely can’t be done by the AVR for some reason, you could consider using programmable logic such as a small CPLD to provide the glue logic and reduce your chip count by 3.

11

Greetings Winston,

winston:
According to Google, the TPIC6C595 is a shift register - could its function be done in software by an AVR instead? Using a bigger AVR to reduce the chip count by 4 would make the PCB far easier to route, and easily 2 layer. If the logic functions absolutely can’t be done by the AVR for some reason, you could consider using programmable logic such as a small CPLD to provide the glue logic and reduce your chip count by 3.

It might help you to read Andy’s original thread [here.

Comments Welcome!](http://forum.sparkfun.com/viewtopic.php?t=10960&start=0)

12

ok, I’ve been using eagle to do the routing and it’s coming along nicely. I’m almost finished routing the single traces, and it looks like I’ve gotten them all on just 2 layers. For the power traces, is it a bad idea to add a +5V plane to one of the sides of the board? I don’t think I’m going to be able to fit my power traces in with the signal traces, so it would be awesome if I could just make one side of the board GND, and the other side +5.

The only reason why I could think of this being a bad idea is either noise levels could increase, or maybe it would be easier for shorts to appear. If it is a bad idea to have a 5V plane, I’ll probably just go to a 4 layer board, but at least this time the middle two layers will be completely dedicated to +5V and GND.

13

You should route critical tracks like ground and Vcc first, then route the signals.

Leon

14

Greetings Andy,

arader:
I’ve been using eagle to do the routing and it’s coming along nicely.

It would help to see your work, can you post your EAGLE files?

arader:
I’m almost finished routing the single traces, and it looks like I’ve gotten them all on just 2 layers. For the power traces, is it a bad idea to add a +5V plane to one of the sides of the board?

Please clarify, do you have two layers or four? A power (or ground)

plane is nothing more than a dedicated layer with solid copper (to

reduce resistance and inductance).

arader:
I don’t think I’m going to be able to fit my power traces in with the signal traces, so it would be awesome if I could just make one side of the board GND, and the other side +5.

Why not make one of two layers a split plane for both power

and ground, and cut into it as needed for the second signal

layer?

arader:
The only reason why I could think of this being a bad idea is either noise levels could increase, or maybe it would be easier for shorts to appear.

The idea behind planes is to reduce noise by reducing the

inductance of the traces. Also, when two or more separate

planes exist they act as a shield and distributed capacitance

to reduce noise, not increase it. The effect is very

subtle unless you are operating at very high frequency and fast

edge clocks (i.e. above 100MHz).

arader:
If it is a bad idea to have a 5V plane, I’ll probably just go to a 4 layer board.

There is a huge jump in cost for a four (or higher)

layer board. This is because the manufacturing process is twice

as complex and the boards can’t be visually inspected (the

cost includes fixtures for electrical bare board testing). A two

layer board is very desireable!

Comments Welcome!

15

bigglez:
Greetings Andy,

Hi :slight_smile:

bigglez:
It would help to see your work, can you post your EAGLE files?

I’m away from the computer with the files right now, so I’ll do my best to explain better. I’ll post the files later tonight.

bigglez:
Please clarify, do you have two layers or four?

Right now I have 2 layers with signal traces in both. I haven’t routed the power and ground lines yet, so I’m trying to figure out the best course of action.

The way I see it, I have two options:

  1. move to a 4 layer board. The pros of this are that I can have a dedicated gnd layer and a dedicated +5 layer. Connecting the power/gnd pins is as easy is adding a via to the correct layer. The cons are cost and complexity as you mentioned. I’d very much like to not need a 4 layer board :slight_smile:

  2. Use eagle’s polygon tool to create a GND plane and a +5v plane. I could either split each of the 2 pcb layers to contain half gnd, half +5, or I could have one layer be the gnd, and the other layer be the +5. I’m concerned that it could be dangerous to have a large area of the board contain 5 volts by causing a short or something. Is this a valid concern? or is it standard design to have a +5V plane on a 2 layer board?

16

It’s more usual to have ground copper pour on one or both sides. As I said previously, you’d have found things much easier if you had sorted out the power distribution first, it is the most important part of the design. It might be best to scrap the esisting design and start again.

Leon

17

Greetings Andy,

arader:
Right now I have 2 layers with signal traces in both. I haven’t routed the power and ground lines yet, so I’m trying to figure out the best course of action. The way I see it, I have two options:

  1. move to a 4 layer board.

  2. Use eagle’s polygon tool to create a GND plane and a +5v plane.

I usually do the power traces first, and then flood unused areas with

a ground polygon, to finish with a two layer design. A key to

“good” (i.e. easy and functional) PCB design is to manipulate

the rats-nest and place the parts in a way to reduce interconnect

crowding. Admittedly, you have limited choices with a piggy-

back design requiring interconnects on all four edges.

You can recover from where you are (an assumption until

I see your WIP), and probably won’t have to start over.

arader:
I’m concerned that it could be dangerous to have a large area of the board contain 5 volts by causing a short or something. Is this a valid concern? or is it standard design to have a +5V plane on a 2 layer board?

The risk of shorts is no greater. During design you can

set the clearance around polygons and trace to trace.

A greater risk of shorts occurs with solder bridges. A solder

mask is very effective at reducing these errors.

Most PCBs would have a ground plane if there’s only room

for one plane type. Ground is the universal reference and

most circuits have more ground connections than supply

connections. (There are exceptions, mostly with high current

and/or high-side driver circuits found in motor drivers,

relay drivers, printer hammer drivers, LED matrices, etc.).

I would favour a few wire links on a two layer board over

a link-free four layer board, for a prototype or budget

limited hobby project.

Looking forward to seeing your WIP layout!

Comments Welcome!

18

yeah, I’m definitely thinking this would have been easier if I started with the power lines first. Anyway, my greatest challenge is due to the fact that I don’t have a single source of power on my board, the lines have to run to each edge in order for me to be able to daisy chain them.

Here’s a screen shot of my board:

http://i25.tinypic.com/iqdmjk.png

I’m definitely confident in the component placing, I went through several iterations before landing on this. I’m super happy that I got all of the other routes on 2 layers, I really didn’t think I was going to be able to :slight_smile:

Here’s the eagle files, let me know if I’ve left anything out: [led_backpack.zip

the zip file contains:

backpack.pro - the project file

backpack.sch - the schematic

backpack.brd - the board

voidsplat.lbr - the custom library parts. Anything not in here is in the default eagle libraries.

thanks for all the great advice and help so far :)](http://voidsplat.org/code/avr/led-matrix/led_backpack.zip)

19

Greetings Andy,

I’ve downloaded and opened the files. No surprises so

far - but you are really painted-into-a-corner on this one!

Additional tools that you can use to ease the design is a

variation on “gate swapping” - a process of swapping like

components to ease the layout. As the parts being swapped

are identical the electrical function is not changed.

Another tool is to swap IO pins on the uC. This can be

resolved with software/firmware IO mapping. The goal is

to remove trace crowding and extra vias.

Next up is to change the physical placement of the IC

packages to reduce crowding. I think you already have

done so, as I see IC packages off-grid and rotated.

There’s nothing wrong with this approach, but in the

days of hand assembly it was unwelcome (too easy to

make a human parts placement error).

arader:
Anyway, my greatest challenge is due to the fact that I don’t have a single source of power on my board, the lines have to run to each edge in order for me to be able to daisy chain them.

Are you willing to change the connector placements?

I know you have a matrix concept with small jumpers

in North, South, East, and West directions. Why not

place the connectors in a parallel mechanical arrangement

(instead of NEWS)? The PCB interconnects will be much

easier, for example, pin1 and pin6 of each connector

are bussed together and would be easy to do with

Poly fills on one layer of the PCB.

arader:
Here’s the eagle files, let me know if I’ve left anything out:

For future reference the EAGLE files are self-contained,

meaning the library parts are copied into the SCH and

BRD files. You don’t need to supply any other library

file to transfer the design to another user.

Comments Welcome!

20

Greetings Andy,

arader:
Here’s the eagle files, let me know if I’ve left anything out

I’m guessing that you created the EAGLE library symbol for

the LED matrix? I saw a couple of problems with it, and

using the [Data Sheet, I’ve corrected it.

Part of the issue is that the dims are in metric, but the

pins are 100mil (standard) pitch. The rows are 24mm

apart (945mils). The layout needs to be very precise as

there is not much room for error. I opened the pad holes

to 30mils (pin diameter is 0.51mm) as I think you’ll

have trouble placing the LED on a PCB if the pads and

holes are too small.

I’ve updated a copy of the PCB layout, and I see that

there is a clearance violation from the LED pads to the

connector pads. The connectors won’t fit on-grid in the

space (assuming the PCB is exactly the same size as

the LED housing).

I can see why you had so many parts off grid - I nudged

the connector off grid and the pad to edge violation has

cleared.

At this point I think you have taken on an expert level

project, and I would not feel comfortable putting my

money on the table to fab this board and expect it to work.

(But I might be less of a risk taker than you).

So far you have a concept and an untried circuit while

pushing the limits of the BatchPCB service. Would it not

make more sense to build a prototype (avoiding PCB

design and layout issues) and test the concept and firmware

as a working model?

Here’s the EAGLE files that I been working on this evening:

http://www.stonard.com/SFE/backpack_1.brd

http://www.stonard.com/SFE/backpack_1.sch

Comments Welcome!](Red 8x8 Square LED Matrix Display Datasheet)