This is a simple AT91SAM7S256 breakout board. I know the schematic is a little messy, but I’m not worried about that right now. I can always clean it up later. I make a lot of home made boards, but due to the number of via’s here, I can’t do that with this, so it’s my first board that I’ll submit to be made, and when it’s ready, I’ll send it to BatchPCB.
Since I’ve never submitted anything before to a board house, I’m hoping you guys can take a look over it and see what I’ve done wrong or can improve.
I’m tired now and I’m sure I missed something simple. I missed Port A 17 pin on the board, I know, but fixing that now would mean a very long time rerouting everything and I’d rather just leave that now. I need to label the power and ground pins as well. It’s passed the SFE DRC already.
Your board generally looks OK. However some silkscreen overlaps pads and/or vias. “AT91SAM7S256” overlaps that part’s pads. Because SMD pads are displayed with the same color as the top traces, it’s difficult to tell where pads and traces meet. So turn on the top solder mask layer (#29 - tStop). The solder mask for a pad is slightly larger than the pad. Because vias are not soldered, you can cover them with solder mask. To do this click Tools/DRC/Masks. Change the “limit” entry from 0mil to 24mil. When the tStop layer is displayed, notice that vias no longer have tStop drawn over each via. The solder mask is actually drawn as a negative. So there won’t be any openings in the solder mask over the vias., but there will still be openings for the pads. This means that any silkscreen that overlaps a via will only lose the little bit over the via’s drill hole.
BTW, I don’t know what BatchPCB’s minimum size if for silkscreen text, but I’ve used size=50mil & ratio=16% for my smallest silkscreen characters.
BTW, I curious where Port A-17 goes., If you would like, I could play with it for a few minutes and see if I could connect it (for free). I need to know what gird you used when routing.
Thanks for all your help. I have made some minor adjustments to the board already. I will upload them later today, before I start updating it with your suggestions. I have a plan for routing the PORT A17 pin and I am going to remove one of the 3.3V lines, but if you want to try routing it yourself, go ahead, but I’d wait for the version I updated yesterday.
Unfortunately I started with 25mil routing before I realized that it just wasn’t going to get everything tight enough together, so I switched to 10mil. I think it knocks a few things out of whack due to that. The original version of the board above has the two long rows of pins on the top of the board, when they should be on the bottom. I’ve corrected that.
The assignement of the pins doesn’t matter, as long as they are labeled on the top, and they don’t physically move from where they are. So you can’t move the rows farther apart or offset them from each other. The plan for this is to plug into a solderless breadboard. I currently have an adapter for doing this with an Olimex sam7 breakout, but I’d like to make this one myself and I think it would be a good test, since the boards I’m making are getting too complex for me to make on my own, and I hate trying to solder my own vias.
Okay. Here’s what I updated yesterday. I haven’t implemented your suggestions, yet. I had to work today. If you want to try and route A17, your free to do so. I’ll be trying to route it to one of the current 3.3v pins when I get a chance to work on this again, tomorrow night.
EDIT: Scratch that. Just taking a quick look at the board again. I was going to route A10 over to the 3.3V pin and move everything around to get A17 in on the bottom row somewhere. Actually, really looking at it, I can see that all the pins can be rerouted better switching some of the assigments around, I might be able to make the pin numbers go in order without much trouble. Oh well. Tomorrow night I’ll rip all that routing up and start again.
I don’t have so much experience, but i think your signal ground is a “little weak”. I mean, at the power connector, the ground signals (bottom layer) are so narrow compared with the rest of the signal ground.
You have to think about the return path of the currents (i know you did it xD), and maybe introducing another .1uF at VddCore is a good idea (preventing a maybe out of supply on them, therefore “killing” your running code), and maybe another .1uF at the Vout of the LD1117.
Thank you very much contributing with your experience.
Thanks for the suggestions! This is the latest brd and sch file. I’ve moved all the silkscreen away from any tStop area and increased the size of the text to minimum 50mil. Ya, I printed out the board and the writing was way too tiny. I’ve also re-netted and rerouted the pins so that they are mostly in order. I’m sure I could get it even better if I spent the time, but this is good enough for me for now.
NoEther: Did you ratsnest the board? I’ve poured copper on the bottom layer with ground and if you hit ratsnest, all the the ground should fill in. There are 5 vias around the uC that are pulling ground up from the bottom layer. I think adding a couple more decoupling caps is a good idea, though.
I figured if I’m sending out, I might as well get as much as I can made up, so I’ll also be submitting my HTTP Server as well. I’ve already made this with toner transfer and it was a serious pain in the @ss. I’ve totally redid the board for getting it fab’ed by an actual board house to make it about a small as I can get it. The rerouted board is about 3/4’s the size of my homemade board.
The board I made, which has different placement and routing, since I need to solder the vias myself. It’s not fully populated. Status LED’s and microSD card slot have not been soldered on, yet.
TheDirty:
NoEther: Did you ratsnest the board? I’ve poured copper on the bottom layer with ground and if you hit ratsnest, all the the ground should fill in. There are 5 vias around the uC that are pulling ground up from the bottom layer. I think adding a couple more decoupling caps is a good idea, though.
So sorry, i didn’t push “ratnest” before “show Vss”, so i only saw the ground signal, not the polygon filled, my fault
About the ground signal question, is more than enough your design, i’m 100% agree now (and before! ofc hehe).
About the decoupling caps, (i know is the normal way to name them xD), but the fuction that i meaned is for feed possibles current peaks on transitories etc.
For decoupling (strictly), only with one cap is “always” enough (depends on your IC and application), if you want more bandwidth, place differents values of caps, like .1 1 10 and so on.
There is a rule for “feeding caps”, and you agree it. The capacitor at Vout (regulator) have to be (at least!) the same or max than all the decoupling capacitors connected to this Vout.
About the photos, they are impressive for a homemade :P, and ofc, it is a pain to craft them :S haha.
Hopefully this is the last update. The board passes SFE’s DRC. I’ve moved all of the pin labels to the inside and made them slightly larger. I’ve added a 0.1uf at the output of the regulator and a second 0.1uf to VDDCore.
So it looks like I can’t submit the HTTP server board. The chip leads have .4mm spacing. That’s 15.75mils from lead to lead. If I make the pad the required 8mils and the space between the required 8mils, it’s all too big by just a hair. I need slightly smaller spacing than the 8mils minimum to use this chip at all. So I’m screwed on this one unless someone can suggest a work-a-round, but this looks pretty much like a show stopper for that board.
I printed out the sam7 board, and looking at it big on the screen really blew out my sense of proportion, because holding the paper cut out to scale in my hand, the thing is really tiny.
TheDirty:
“If I make the pad the required 8mils and the space between the required 8mils, it’s all too big by just a hair. I need slightly smaller spacing than the 8mils minimum to use this chip at all. So I’m screwed on this one unless someone can suggest a work-a-round, but this looks pretty much like a show stopper for that board.”
Ya, it looks like a fairly common problem. I can’t get the thing to pass the SFE DRC, because the minimum 8mil spaces and 8mil traces are just very slightly too large for .4mm leads. I would need 7.87mil traces and spacing.
Ironically, it looks like this is a board I can do myself at home (with altered layout to solder the vias), but BatchPCB can’t do, unless I submit it as a 4 layer board which allows smaller traces.
Well, I’m finally going to submit these things. I’ve wanted to verify all the stuff I’m doing with the SAM7 chips before I sent in the final designs, and I’m pretty comfortable with what I have.
I realize I incorrectly put the year as 2008 on all my previous files. Oh well.
I couldn’t submit my simpler 8bit microcontroller + WizNet W5100 design because of the 0.4mm lead spacing, so I went crazy and designed a W5300 project with another SAM7256.
