#ifndef EMAC_PIO_SODR
#define EMAC_PIO_SODR PIOB_SODR
#endif
static int EmacReset(u_long tmo)
{
u_short phyval;
outr(PMC_PCER, _BV(PIOA_ID));
outr(PMC_PCER, _BV(PIOB_ID));
outr(PMC_PCER, _BV(EMAC_ID));
/* Disable RMII and TESTMODE by disabling pull-ups. */
outr(EMAC_PIO_PUDR, _BV(PHY_COL_RMII_BIT) | _BV(PHY_RXDV_TESTMODE_BIT));
/* Disable PHY power down. */
outr(EMAC_PIO_PER, _BV(PHY_PWRDN_BIT));
outr(EMAC_PIO_OER, _BV(PHY_PWRDN_BIT));
outr(EMAC_PIO_SODR, _BV(PHY_PWRDN_BIT));
#if 0
#define RSTC_CR (RSTC_BASE + 0x00) /*!< \brief Reset controller control register address. */
#define RSTC_PROCRST 0x00000001 /*!< \brief Processor reset. */
#define RSTC_PERRST 0x00000004 /*!< \brief Peripheral reset. */
#define RSTC_EXTRST 0x00000008 /*!< \brief External reset. */
#define RSTC_KEY 0xA5000000 /*!< \brief Password. */
#define RSTC_URSTEN 0x00000001 /*!< \brief User reset enable. */
#endif
/* Toggle external hardware reset pin. */
outr(RSTC_MR, RSTC_KEY | (unsigned long)( 0x01 << 8 ));
outr(RSTC_CR, RSTC_KEY | RSTC_EXTRST);
while ((inr(RSTC_SR) & RSTC_NRSTL) == 0);
/* Configure MII port. */
outr(EMAC_PIO_ASR, PHY_MII_PINS_A);
outr(EMAC_PIO_BSR, PHY_MII_PINS_B);
outr(EMAC_PIO_PDR, PHY_MII_PINS_A | PHY_MII_PINS_B);
/* Enable management port. */
outr(EMAC_NCR, inr(EMAC_NCR) | EMAC_MPE);
//outr(EMAC_NCFGR, inr(EMAC_NCFGR) | EMAC_CLK_HCLK_64) ; // Original from Ethernut-4.2.1
outr(EMAC_NCFGR, inr(EMAC_NCFGR) | EMAC_CLK_HCLK_32);
/* Wait for PHY ready. */
NutDelay(255);
/* Clear MII isolate. */
phyval = phy_inw(NIC_PHY_BMCR);
phy_outw(NIC_PHY_BMCR, phy_inw(NIC_PHY_BMCR) & ~NIC_PHY_BMCR_ISOLATE);
/*
- Read link partner abilities and configure EMAC.
*/
phyval = phy_inw(NIC_PHY_ANLPAR);
if (phyval & NIC_PHY_ANEG_TX_FDX) {
/* 100Mb full duplex. */
outr(EMAC_NCFGR, inr(EMAC_NCFGR) | EMAC_SPD | EMAC_FD);
}
else if (phyval & NIC_PHY_ANEG_TX_HDX) {
/* 100Mb half duplex. */
outr(EMAC_NCFGR, (inr(EMAC_NCFGR) & ~EMAC_FD) | EMAC_SPD);
}
else if (phyval & NIC_PHY_ANEG_10_FDX) {
/* 10Mb full duplex. */
outr(EMAC_NCFGR, (inr(EMAC_NCFGR) & ~EMAC_SPD) | EMAC_FD);
}
else {
/* 10Mb half duplex. */
outr(EMAC_NCFGR, inr(EMAC_NCFGR) & ~(EMAC_SPD | EMAC_FD));
}
/* Disable management port. */
outr(EMAC_NCR, inr(EMAC_NCR) & ~EMAC_MPE);
/* Enable receive and transmit clocks and set MII mode. */
outr(EMAC_USRIO, EMAC_CLKEN);
return 0;
}