We have an engineering prototype where we have selected an Ethernet PHY using a 128-pin 17x23mm footprint (pins around the sides). Unfortunately, there are no drivers for this PHY for the chip we connected it to; thus we need to use a different PHY. The PHY we want to use is a smaller 64-pin 9mm x 9mm BGA.
We are thinking of making a daughter PCB that fits into the 128-pin footprint, and we can solder it in the footprint on our board. On the daughter PCB we can have the footprint of the new PHY we want to use and connect the pins accordingly (possibly routing would be all over the place).
Based on the footprint below, do you think this is possible?
What is the best way to make a PCB with pins on the sides of it that would fit into a different footprint? (i.e, how do we specify we want pads on the sides or bottom of the PCB we make, so we can just solder it in to the old footprint?)
If I need to use multiple layers, can I? What software do I need?
MII/RMII/SMII/GMII/RGMII are all standard - that shouldn’t be a problem.
The only issue would be setting the correct MIIM regs - and thats pretty trivial. You could even throw an avr or something on a breadboard with wires for the MDIO/MDC lines if for some reason you absolutely cannot write any code for the main chip.
I think either of those solutions would be easier than trying to make an adapter.
Er, and its pretty hard to fab a PCB with pads on the sides. The only way I know of is to have drill hits that you route through, but that probably wouldn’t work for anything fine-pitch smt.
We thought that the drivers would be compatible, but unfortunately they are not. We are also using a custom ASIC, so there are not many drivers written for individual PHYs.
Initially we had thought that only the registers are differing, but the FAE is telling us that this is not the case. We are able to modify the driver to change the register bits, but since more is required we are considering an adapter.
I am woried about two things: how to make the pcb so we can solder the adapter into the 0.5mm pitch footprint; and how if the routing will be possible (from batch pcb) since the new phy is on a BGA.