Philba:
better. You still have some right angles but it will probably work. Have you run DRC on it? There are some things that look kind of close.
Thanks. The feedback you guys gave me was awesome. This circuit will only be switching at 256 Hz, which is “slow”, but the FET will be switching anywhere from 0.5Amps to about 4Amps, which is why I made the FET traces larger (I hope this is enough), and why I have a separate ground plane for the uP and a second more confined ground plane for the FET.
Yes, the DRC gives me two sets of errors:
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Dimension errors, where the outer perimeter (layer 20 for the circle) is a tad too close in a a few places. This does not worry me, since the edge of the board will be protected from touching anything - no chance for a short.
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Stop Mask errors, all of them in layer 29. Most of these seem to come from very tiny overlaps (nothing much), but picked up by the DRC. Do I need to worry about these? What can I do change to minimize these errors?
Will