Impedance control - CCLK line for a Spartan-6 FPGA

Community PCB Design
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Hi all

A bit of background: I’m an amateur hardware hacker, and so far the closest I’ve got to high-speed digital is using the Wiznet W5100 ethernet IC on one of my boards (no - not the WIZ-whatever breakout board, but the actual chip on my own layout) - without any problems whatsoever. The highest frequencies on that board encountered were the 25MHz crystal and the ethernet TX/RX pairs (100Mbit ethernet having a fundamental frequency of ~33MHz, 10 meg being 20MHz using Manchester encoding). I did this on a four layer board. My strategy for this was to just keep everything high speed very short - the crystal as close as I could get to the W5100, and the ethernet magjack as close as I could possibly get to the W5100.

I’m mulling over an idea for a project that would involve using a Spartan-6 FPGA - probably an LX9 in a TQFP-144 package. I’ve not got as far yet as even thinking of a schematic, but I’m doing some background reading. As a rank amateur, one thing I’ve found slightly terrifying in Xilinx’s documentation is that the CCLK (configuration clock) from the FPGA to the platform flash (where the configuration is stored) must have a characteristic impedance of 50 ohms. They go on to describe a termination method using two 100R resistors (one to Vcc, the other to ground) coming off the side of the CCLK net and a few general bits of advice.

From what I’ve read so far, the characteristic impedance of a PCB trace depends largely on its width and how far its separated from the ground plane (and I read somewhere else that the power plane may be considered equivalent). I’ve read other documents which make it an extremely complex subject (making the subject of impedance control look very complex and very expensive to do). Furthermore, I’ve just been looking at the Digilent Spartan-3 starter kit board I have and its schematics to see what Digilent did. On their CCLK line they’ve put a 51 ohm resistor in series with the FPGA and the platform flash. The CCLK line itself seems to take a fairly circuitous route - it comes out the bottom of the FPGA on the side furthest from the platform flash, through the 51R resistor, then through a via into some internal layer before appearing through another via close to the platform flash - so they don’t do anything at all like what Xilinx suggests in their documentation.

Further reading shows that the highest CCLK frequency is 26MHz. A rough back-of-the-envelope calculation would estimate that the wavelength in copper at 26MHz would be on the order of 8 metres, and 10% of that being 80cm, so the trace would have to be absurdly long to be a transmission line. Or does the CCLK line turn into a transmission line because of the speed the edges rise and fall rather than its actual frequency? (Perhaps that’s why Digilent have put in a series resistor - to reduce the rise and fall times of the clock as it has to charge and discharge the parasitics…)

How critical is this? If I keep the trace short (say, less than 25mm between the FPGA’s CCLK pin and the platform flash’s CLK pin) - so long as it’s the right width and has the termination that Xilinx suggests - or do what Digilent has done with the 51 ohm resistor, am I likely to make a reliable circuit? Or do I have to start getting expensive engineering resources engaged at the PCB fab stage (which basically kills the project idea dead)? I note one PCB fabricator (PCB CART) has a check box for “impedance control”, but it doesn’t elaborate any more. (I am planning to use iTead’s service, since a few people have recommended it). Am I just making a mountain out of a molehill? If anyone has experience with making circuits using Xilinx FPGAs and the platform flash, I’m very interested to hear what you did.

I’m not intending to use the CCLK pin for anything after the FPGA has been configured, so the CCLK trace will have nothing except the platform flash on it. I’m intending to use a 4 layer board, with the inner layers being power and ground planes.

As a follow-up - talking of power planes - where you have multiple voltages (such as the core voltage for the FPGA and then the IO voltage for the FPGA), what’s a good practise for doing this if you don’t have enough layers to dedicate each voltage its own uninterrupted power plane?

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The Xilinx forum is the best place for questions like those.

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Well, I didn’t ask there because most of it’s not specific to Xilinx, it’s general “what to do about impedance control”. Perhaps I didn’t write a good question. I suspect the Xilinx forum would tell me to go to a general PCB design forum :slight_smile: (In fact, reading through the forum most of the responses to this kind of question are “Do as Xilinx says” or "Simulate it using this software costing $tensofthousands and see if it’s OK. Perhaps those are the only reasonable answers).

I also have to imagine this information is going to be useful for other Sparkfun forum users - after all we’re seing people do microcontroller projects with higher frequency signals and they may benefit from knowing the potential issues of square wave clock signals running in the low tens of MHz.

OK - I’ll rephrase my question - forget Xilinx for a moment, here are the general PCB layout questions:

  • Why would a signal with a max frequency of 26MHz need a 50 ohm impedance controlled PCB trace with Thevenin termination? A rough back of the envelope calculation says that a trace carrying a signal of this frequency does not become a transmission line until it’s about 80cm long. Is the need for impedance control due to the higher frequency harmonics of this signal?

  • (We can forget this question if it’s likely to be something specific to the IC in question, and not something that can be applied generally). I’ve seen an example of the circuit in the real world which has at least two vias (in other words, impedance discontinuities), but what the designer did was to stick a 51 ohm resistor in series with the signal close to where it comes out of the IC in question. That designer didn’t use Thevenin termination. This is on a mass-produced board which functions perfectly reliably. Are there any caveats to this approach?

  • If you do need to have impedance control done on a PCB, it looks to me like an expensive process requiring engineering resource at the PCB house, turning a perfectly feasable 10 boards for $99 type project to something that will cost $thousands. PCB CART has a check box for impedance control if you order PCBs from them. What does a PCB house do if you ask for impedance control?

  • As a follow up, if you have multiple supply voltages, are there any accepted practises as to what to do with your power plane if you don’t have enough layers to dedicate a power plane to each voltage? (Especially if it’s only one IC that requires the different voltages).

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The series termination is there to dampen ringing for the falling and rising edges, this is placed at the source of the signal, it also helps in reducing the current draw at the time the edge transitions.

Most high speed single ended signals that travel over a certain length tend to always have series terminations, if you have a board and a scope, you can swap out values and see the change to the waveform as you change values.

The power plane, if you have only one plane to route on really comes down to a few things.

try to organize the different components into groups of that same power rail if possible. This is not always possible though.

depending on the device type and current draw, power can be routed on a signal plane, if the device only draws a small amount of current then it does not really need to be wired directly to a plane, a trace of the appropriate size is fine. Just make sure you have decoupling caps as close to the power pins as possible. And also keep the traces from the caps to any vias as short as possible, this will help at higher frequency load changes like you would see from a CPU or FPGA, etc.

Hope this helps,

Croc4

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You’re worrying about nothing. CCLK isn’t very fast at all. I think it starts at 2.5 MHz and then changes based on bitgen settings, which is Xilinx stuff that I know nothing about.

I assume your signal isn’t going to travel more than an inch or so. Differences between 12mil core vs 15mil core, or between a 5mil trace and a 6 mil trace, or FR4 vs something else just don’t matter at those frequencies and length of trace.

Anything less than 100 MHz isn’t that big of a deal – keep traces short, and terminate it to 50R like you’re supposed to do. That either means put a 50R resistor to ground, or two 100R resistors to your power rail. I’d recommend the former. Other people have explained the purpose of the resistors – basically, they’re to avoid ringing. The input pin the signal is flowing into is a FET, which is very high impedance, so signals will “bounce” off of it (since it doesn’t really draw much current at all). You can absorb that “bounce” by terminating it with a resistor.

I’ve laid out boards with 400 MHz parallel memory interfaces, and I’ve never had to worry about controlled impedances. If the impedances aren’t matched, you’ll either get some signal reflection (manifested as noise) if the impedance is too high, or you’ll stress your source driver device with excess current, if the impedance is too low.

The only time you need to order an impedance-matched board is if you’re doing high-frequency (>500 MHz) PCB antennas.

I hope this makes you feel a little more comfortable!

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Thanks for the replies. I’ve since found more reading material on the subject of transmission lines (there was a very interesting one from Cypress for their clock generator ICs which had a lot of good information). I’m always a bit wary of deviating from the advice given by the engineers of a particular device though :slight_smile:

Since posting this I’ve found out from a friend who’s doing some FPGA stuff that he’s just completed a PCB with a Spartan-3 on it, which is just a two layer board - and he’s had no trouble at all with the CCLK line (he read about the controlled impedance advice in the Xilinx configuration manual only after sending off to get the PCBs made). He asked colleagues at the university what they did with their CCLK lines and they all said that they had done nothing special and it had just worked.

So perhaps Xilinx has this layout advice so that the device will work even in the worst case scenario, given that the CCLK pin can later be reused as an I/O and thus end up being routed all over the place. (I don’t intend to reuse CCLK, and my intention will be to get the platform flash as close as practical to the FPGA’s CCLK pin)

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Hi,

Xilinx’s documentation is that the CCLK … must have a characteristic impedance of 50 ohms.

This is a new recommendation from Xilinx. With older FPGA (SPARTAN-3), Xilinx doesn’t suggest any termination adaptation.

does the CCLK line turn into a transmission line because of the speed the edges rise and fall rather than its actual frequency?

Yes, you have to take in account the rise and fall time of the signal. In past, I had adaptation problems with a 19 MHz clock…

the designer did was to stick a 51 ohm resistor in series with the signal close to where it comes out of the IC in question. That designer didn’t use Thevenin termination.

The Thevenin termination allows to fine tune the adaptation more than with a serial dump resistor. This may be useful in some cases, specially if you don’t simulate your PCB.

are there any accepted practises as to what to do with your power plane if you don’t have enough layers to dedicate a power plane to each voltage?

You can do a plane inside another plane (avoid to do it in the GND plane), or a partial plane on a signal layer. For example for the FPGA’s 1.2 V, if used only by the FPGA, you can do a 1.2 V plane located under the FPGA.

You can find an example of a design with a SPARATAN-6 and partial planes at :

http://www.ohwr.org/projects/timex3/wiki

It’s still under progress, but it’s open hardware and made with KiCad so you can check it easily.

Also, you can check in the same repository the Rhino project :

http://www.ohwr.org/projects/rhino-hardware-01/wiki

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JPR75:
This is a new recommendation from Xilinx. With older FPGA (SPARTAN-3), Xilinx doesn’t suggest any termination adaptation.

It’s a recommendation for the Spartan-3, too - see page 58 and on of the Spartan-3 configuration user manual: http://www.xilinx.com/support/documenta … /ug332.pdf