OpenOCD init stage

Development Boards MicroMod
1

Hi Everybody,

I am working with Olimex LPC-2478STK board. I’d like to init external SDRAM to debug it. Because I am completely new to OpenOCD I decided to start from something really simple- turning on a led. So, in Eclipse’s Debug Configuration (I use Zylin Plugin) I set Initialize commands:

target remote localhost:3333
mww 0x3FFFC020 0x42000 # set direction port for leds
mww 0x3FFFC03C 0x42000 # turn on leds

In Run commands I have this:

monitor soft_reset_halt
monitor arm7_9 sw_bkpts enable
load out/soft.elf
symbol-file out/soft.elf

This works- when I run the project debug session I can see that the memory cells are initalized properly, because leds are on. Then my program starts and do its stuff.

But I saw in the board examples that it’s possible to init memory cells in *cfg files. So, I moved my initialization commands to my lpc2478.cfg file:

$_TARGETNAME configure -event reset-init {
	# Force target into ARM state
	arm core_state arm
	# Do not remap 0x0000-0x0020 to anything but the Flash
	mwb 0xE01FC040 0x01
        # set leds here
	mww 0x3FFFC020 0x42000
	mww 0x3FFFC03C 0x42000 
}

Now it does not work- my leds are off now when fireing the debug session. My questions:

  1. Running the OpenOcd as a deamon in Eclipse cannot set the memory cells? If yes how that’s possible that those config board files works? I mean they are able to set for example EMC. In the Guide there is a note: “Any initialization sequence to enable that external flash or SDRAM should be found in the board file”, so I thought that by calling:
-f interface\my_dongle.cfg -f board\my_board.cfg

and running OpenOcd I’d get required memory cells initialized.

  1. Running debug session can only init the uc (my leds or EMC)?

If someone could explain my missing point, I’d appreciate.

Regards,

Kuba

2

hi,

If you wanna the procedure of “$_TARGETNAME configure -event reset-init” run, you have to add these commands at the end of configuration file:

init
reset init
3

Unfortunately, those commands did not work for me. I’ve also tried to invoke -event reset-init by adding to the “Initialize commands”

monitor reset init

Moreover I add a function:

$_TARGETNAME configure -event gdb-attach {
         echo "Reset..."
         reset init
     }

without success, however. Is out there any Guy, who invokes successfully a board config file with some peripherals initialization? If yes, how to do this?

Regards,

Kuba

4

Ok- the commands works. An interesting thing is that putting

init
reset init

directly do the Eclipse “Initialize commands” I got the leds on, even before I run the debbug session. Placing them in my script *.cfg causes that I have the leds on but after running the session.

Anyway, I found here: http://www.mail-archive.com/openocd-dev … 14811.html a board file for LPC 2478 with external SDRAM and some additional peripherals. I need only SDRAM, so that’s how my board file looks like:

# delays on reset lines
jtag_nsrst_delay 100
jtag_ntrst_delay 1

# adaptive JTAG clocking through RTCK.
jtag_khz 1

# Target device: LPC2478
set CCLK 72000
source [find target/lpc2478sdram.cfg]

# working area will help speeding the flash programming
$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0

# read register procedure
proc read_register {register} {
    set result ""
    mem2array result 32 $register 1
    return $result(0)
}

# set PLL
proc enable_pll {} {
	# check PLL status- if connected then disconnect it
	#if {[expr [read_register 0xE01FC088] & 0x2000000] == 3} {
	# PLLCON = 1;
	#	mww 0xE01FC080 0x1	
	# pllFeed();
	#	mww 0xE01FC08C 0xAA				
	#	mww 0xE01FC08C 0x55
	#}
	# disable PLL as it can be already enabled
	# PLLCON = 0;
	mww 0xE01FC080 0x0		
	# pllFeed();
	mww 0xE01FC08C 0xAA				
	mww 0xE01FC08C 0x55
	
	# set 288MHz PLL from internal RC 
	# SCS |= 0x20;
	mww 0xE01FC1A0 0x20	
	# while( !(SCS & 0x40) );	
	sleep 100	
	# CLKSRCSEL = 0x1;	
	mww 0xE01FC10C 0x1
	# PLLCFG: N=0, M=11
	mww 0xE01FC084 0xB
	# pllFeed();	
	mww 0xE01FC08C 0xAA				
	mww 0xE01FC08C 0x55
	# PLLCON = 3;
	mww 0xE01FC080 0x00000003 
	# pllFeed();
    mww 0xE01FC08C 0x000000AA       
    mww 0xE01FC08C 0x00000055  
	 # CCLKCFG: divide by 4 (72 MHz)
	mww 0xE01FC104 0x00000003 
	# while ( ((PLLSTAT & (1 << 26)) == 0) );	
    sleep 100	
	# PLLCON = 3;	
    mww 0xE01FC080 0x00000003  
	# pllFeed();	
    mww 0xE01FC08C 0x000000AA       
    mww 0xE01FC08C 0x00000055  
	# while ( ((PLLSTAT & (1 << 25)) == 0) );
	sleep 100						
}

$_TARGETNAME configure -event reset-start {
	jtag_khz 500
 }
 
 $_TARGETNAME configure -event reset-init {
	arm core_state arm
	# Speed up downloads by using DCC transfer
	arm7_9 dcc_downloads enable		
	arm7_9 fast_memory_access enable
	
	# Peripheral clocks
	# PCONP = reset value
    mww 0xE01FC0C4 0x04280FFE       
	
	# Map the user flash to the vector table area (0x00...0x3F)
	# MEMMAP = MEMMAP_MAP_FLASH
    mww 0xE01FC040 0x00000001       
	
	# Memory accelerator module
	# MAMTIM: 3 clock cycles
    mww 0xE01FC004 0x00000004 
	# MAMCR: fully enabled
    mww 0xE01FC000 0x00000002       
	
	enable_pll
	#jtag_khz 1000
	
	# SDRAM configuration for 2 x Samsung K4S561632J-UC75
	puts "Configuring SDRAM"
	# setup PINSELs
	# PINSEL5 |= 0x55010115; //BIN32(01010101,00000001,00000001,00010101);
	mww 0xE002C014 0x55010115
	# PINMODE5|= 0xAA02022A; //BIN32(10101010,00000010,00000010,00101010);
	mww 0xE002C054 0xAA02022A
	# PINSEL6  = 0x55555555; //BIN32(01010101,01010101,01010101,01010101);	
	mww 0xE002C018 0x55555555
	# PINMODE6 = 0xAAAAAAAA; //BIN32(10101010,10101010,10101010,10101010);
	mww 0xE002C058 0xAAAAAAAA
	# PINSEL7  = 0x55555555; //BIN32(01010101,01010101,01010101,01010101);
	mww 0xE002C01C 0x55555555	
	# PINMODE7 = 0xAAAAAAAA; //BIN32(10101010,10101010,10101010,10101010);
	mww 0xE002C05C 0xAAAAAAAA	
	# PINSEL8 |= 0x15555555; //BIN32(00010101,01010101,01010101,01010101);
	mww 0xE002C020 0x15555555	
	# PINMODE8|= 0x2AAAAAAA; //BIN32(00101010,10101010,10101010,10101010);
	mww 0xE002C060 0x2AAAAAAA
	# PINSEL9 |= 0x00040000; //BIN32(00000000,00000100,00000000,00000000);
	mww 0xE002C024 0x00040000	
	# PINMODE9|= 0x00080000; //BIN32(00000000,00001000,00000000,00000000);
	mww 0xE002C064 0x00080000		
	
	# PCONP |= PCONP_PCEMC;
	mww 0xE01FC0C4 0x800	
	# EMC_CTRL = EMC_CTRL_EMC_ENABLE;
	mww 0xFFE08000 0x1	
	# EMC_DYN_RD_CFG = 1;
	mww 0xFFE08028 0x1	
	# EMC_DYN_RASCAS0 = 0x303; 
	mww 0xFFE08104 0x303
	# EMC_DYN_RP = P2C(SDRAM_TRP);	
	mww 0xFFE08030 0x2	
	# EMC_DYN_RAS = P2C(SDRAM_TRAS);
	mww 0xFFE08034 0x4		
	# EMC_DYN_SREX = P2C(SDRAM_TXSR);
	mww 0xFFE08038 0x5	
	# EMC_DYN_APR = SDRAM_TAPR;	
	mww 0xFFE0803C 0x1	
	# EMC_DYN_DAL = SDRAM_TDAL+P2C(SDRAM_TRP);
	mww 0xFFE08040 0x5	
	# EMC_DYN_WR = SDRAM_TWR;
	mww 0xFFE08044 0x3	
	# EMC_DYN_RC = P2C(SDRAM_TRC);
	mww 0xFFE08048 0x5	
	# EMC_DYN_RFC = P2C(SDRAM_TRFC);
	mww 0xFFE0804C 0x5	
	# EMC_DYN_XSR = P2C(SDRAM_TXSR);
	mww 0xFFE08050 0x5	
	# EMC_DYN_RRD = P2C(SDRAM_TRRD);	
	mww 0xFFE08054 0x2		
	# EMC_DYN_MRD = SDRAM_TMRD;
	mww 0xFFE08058 0x3	
	# EMC_DYN_CFG0	=(1 << 14)|(0 << 12)|(3 << 9)|(1 << 7); 
	mww 0xFFE08100 0x4680			
	
	# EMC_DYN_CTRL	= 0x00000183;
	mww 0xFFE08020 0x00000183	
	# DELAY
	sleep 100		
	# EMC_DYN_CTRL	= 0x00000103;
	mww 0xFFE08020 0x00000103	
	# EMC_DYN_RFSH	= 1;
	mww 0xFFE08024 0x1
	# DELAY
	sleep 100	
	# EMC_DYN_RFSH	= P2C(SDRAM_REFRESH) >> 4;
	mww 0xFFE08024 0x23	
	# EMC_DYN_CTRL	= 0x00000083;
	mww 0xFFE08020 0x00000083	
	# dummy = *((volatile uint32_t *) (SDRAM_BASE_ADDR | (0x32 << 13)));
	mdw 0xA0064000 1	
	# EMC_DYN_CTRL = 0x00000000;
	mww 0xFFE08020 0x00000000	
	# EMC_DYN_CFG0 |= 0x00080000;
	mww 0xFFE08100 0x84680				 
}

# working area
$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x10000 -work-area-backup 0

Target file:

if { [info exists CHIPNAME] } {
	set  _CHIPNAME $CHIPNAME
} else {
	set  _CHIPNAME lpc2478
}

if { [info exists ENDIAN] } {
	set  _ENDIAN $ENDIAN
} else {
	set  _ENDIAN little
}

if { [info exists CPUTAPID ] } {
	set _CPUTAPID $CPUTAPID
} else {
	set _CPUTAPID 0x4f1f0f0f
}

# added for SDRAM 
if { [info exists CCLK ] } {
	set _CCLK $CCLK
} else {
    error "You must specify the CCLK that will be used for flash programming!"
}

# Delays on reset lines
#jtag_nsrst_delay 200
#jtag_ntrst_delay 200

# LPC2000 -> SRST causes TRST
reset_config trst_and_srst separate #trst_and_srst srst_pulls_trst

# Add TAP(s) to the Scan Chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

# Add CPU target(s)
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4

# Add work area- to speed up downloads
# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
#$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0

# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 $_CCLK calc_checksum

My Eclipse “Initialize commands”:

target remote localhost:3333
monitor init
monitor reset init
monitor soft_reset_halt
load out/soft.elf

I have GDB error “Load failed”:

load out/soft.elf
&"load out/soft.elf\n"
~"Loading section .sdram, size 0x8c lma 0xa0000000\n"
Loading section .sdram, size 0x8c lma 0xa0000000
&"Load failed\n"
963^error,msg="Load failed"
(gdb) 
Load failed

and that’s the OpenOcd output:

Open On-Chip Debugger 0.4.0 (2010-11-23-14:20)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.berlios.de/doc/doxygen/bugs.html
jtag_nsrst_delay: 100
jtag_ntrst_delay: 1
1 kHz
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
Info : clock speed 1 kHz
Info : JTAG tap: lpc2478.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
Info : Embedded ICE version 7
Error: EmbeddedICE v7 handling might be broken
Info : lpc2478.cpu: hardware has 2 breakpoint/watchpoint units
Info : accepting 'gdb' connection from 0
Warn : acknowledgment received, but no packet pending
undefined debug reason 6 - target needs reset
Warn : target not halted
500 kHz
Info : JTAG tap: lpc2478.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
core state: ARM
dcc downloads are enabled
fast memory access is enabled
0xa0064000: 00000083 
requesting target halt and executing a soft reset
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
Warn : ThumbEE -- incomplete support
Error: timed out while waiting for target debug-running
Error: unexpected error -4

Does anyone used this board config file and know where the problem is?

Regards,

Kuba