And, a forth…
Okay, I now understand the placement of C1… The instructions show C1 close to pin #1/MCLR… So, please teach me as to why it should be near the USB. I understand what a decoupling capacitor does… I thought C1 was to limit interference and, the closer to pin #1, the better.
I’ll get it moved and repost. Thanks for everyone’s great help!
Like I said, just use mine and edit the silkscreen and you’re done. It is better when the cap is close to the supply pins, but not when the ground path is really long. When it does pick up noise, where do you think it goes? Into ground… If the ground path is long, the noise is more susceptible to return to the supply.
That makes sense. Thanks.
C1 doesn’t have any connection to pin 1; it is wired as a bypass cap. If the part is a PIC18F2550 family part, C4 needs to be a 220nf cap; that would be a ceramic, not electrolytic. Likewise, I would use ceramic for the two 100n bypass caps, one between pins 11 and 12, and one between pins 31 and 32. The footprint would be the same one you use for C2 and C3.
Can you nudge the PIC up a bit to run Vcc from the USB connector around the left of the connector and around the lower edge of the board to connect to pin 32? That would let pin 31 connect to the pour under the chip. The most important is a good low-inductance connection between the bypass caps and the Vdd/Vss pins of the PIC. The second most important is the connection to the USB connector. The connections to the buttons and LED is the least important.
I would even consider using a topside trace to connect pin 11 to pin 32, with suitably-sized vias, or a jumper like J1. That way, if you have the board fab’ed, you can do it double-sided. If you hand-etch, then replace that top-side trace with a jumper made from a cut-off resistor lead. If you go that route, I’d add the top-side trace connecting the two pads for J1 as well.
Mike, you are right on time! I did stray from the original schematic, which, I think, is more inline with your instructions. I have been concerned about my changes and I was about to post in this regard. Yes, the chip is in the PIC18F family.
I wholly admit that I know very little about circuit design. I am much more of a find-a-schematic-and-solder-it-up kind of guy. But, I am trying to learn about design.
See screen shot. The original schematic calls for a 0.1u cap on the supply leg at the USB. And, it calls for a 0.1 cap (plus the 10u cap) on pin #1/MCLR. The schematic does not call for caps on the two VDD pins and I know a proper design should have decoupling caps on the supply pins.
I had assumed that the cap at the USB was meant to decouple both supply pins and was just not placed well. I had combined the decoupling caps for Pin #1 and the two needed for the supply pins (thinking that a 0.47u cap would have enough capacity for all three legs [3 x 0.1 = 0.3; 0.3 < 0.47]) and placed it closer to the pins in need.
I understand, now, that the cap on the USB was to limit interference. And, you have explained about the bypass cap.
My idea for the design is to accomplish several things; minimize the width of the board, place the passive components under the chip socket and make it Noob friendly (one-sided and big traces/clearances.)
So, I still have some questions…
-The only reason I am using the electrolytic cap for decoupling is that I have it on hand. I thought that it was okay to use an electrolytic in the place of a ceramic, but not vice versa. Do I have that right?
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Can the three (Pin #1 plus 2 for VDD’s) decoupling caps be combined?
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Is the C4 0.1 USB cap of adequate capacity?
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Should C1 be placed near Pin #1, or the USB connector?
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Maybe summarize the needed changes to the author’s schematic to keep me straight.
I apologize for having not posted the author’s schematic. I should have done that from the start. Here it is. I am not concerned with the LEDs.
While waiting for your reply, I practiced learning Eagle by taking a shot at updating the project in the manner that I thought you might instruct me. See Attached…
I created a new device for C5 and gave it a stance wide enough to jump over the D+/- traces.
I am having trouble trashing the dimension lines on the board.
Thank you for your continued help!
From my research, it appears that the value of C4 should be 0.47u. I forgot to change the value of C5. It should be 0.1u.
C4 is a [decoupling Cap.](Decoupling capacitor - Wikipedia)
Here is the latest, and, hopefully, the last, version of the board. Various compromises robbed it of visual elegance. However, the chip is stacked on top of the components, so that is less important.
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J1 was put on the diagonal to allow J3 to be added.*
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J3 was added to straighten, and shorten, the ground path.
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C4 was moved to the right, to preserve the ground plane above J1.
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The decoupling cap that was next to the USB has been removed to allow placement of J1 and J3.
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C5 has been centrally located and increased in value. Testing will show if it is sufficient to services the USB, two Vdds and Pin #1/MCLR.
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C1 was moved to the left, and away from, Pin #1 to allow its ground pin to access the ground plane. Testing will determine if it close enough to Pin #1.
- There is no J2. The board will be renumbered.
Unless there are additional needed changes, I will move forward to make a prototype. Thank you so much for all your help and support!
Can I suggest a GND link around\under C5 to link those 2 grounds together rather than a loop around the outside. (Like J3)
That is a good suggestion, Mattylad. Thank you for helping me. Another jumper, there, would be a good thing.
I forgot to highlight the ground plane. It makes a clear path, outside of the chip. It services the Buttons and LED. The ground on those components is not critical to the continuous operations of the circuit.
I have reworked the layout so many times that making more changes does not sound like any fun, so I think I will build/test it, as is, and add your jumper, if needed.