Over the weekend I submitted a design to BatchPCB for a PSU created using Eagle. It failed DRC highlighting the ground plane, I then resubmitted it after increasing the isolation but it still fails.
I suspect it could be the thermals but I do no know how to make them bigger; or it could be something else I am missing.
Over the weekend I submitted a design to BatchPCB for a PSU created using Eagle. It failed DRC highlighting the ground plane, I then resubmitted it after increasing the isolation but it still fails.
I suspect it could be the thermals but I do no know how to make them bigger; or it could be something else I am missing.
I know the board layout is not the best, but I tried using the thickest tracks I could.
Any advise?
Thanks
Adriaan
EAGLE v5.6 reported TONS of DRC errors - mostly due to the sense pads for the current monitor. Overlapping holes may or may not be accepted by your board house. You may have to make a slot instead. Check with your board house (BatchPCB?) to see how they want to handle this. Also, there vias that are too close to the traces; and a trace that connects to pin-2 of Power connector, is too close to the edge of the board. Increase the width of your polygons - 16 mil (0.016") is a good value. A width of 0 is what is causing BatchPCB’s bot to complain. Because you have a copper pour (polygon) for GND on the bottom, you don’t need individual GND traces on the bottom.
I know the current sensor is a bit “dodgy” but after following gussy’s advice to change the ground polygon width from 0 to 10mil it made the thermals thicker and it passed the DRC bot’s scrutiny.
Another thing I noticed was that the resulting cam files were much smaller in size. I wonder how cam processor export’s 0mil polygon’s that are filled.
AdiCPT:
I know the current sensor is a bit “dodgy” but after following gussy’s advice to change the ground polygon width from 0 to 10mil it made the thermals thicker and it passed the DRC bot’s scrutiny.
Another thing I noticed was that the resulting cam files were much smaller in size. I wonder how cam processor export’s 0mil polygon’s that are filled.
Well, imagine that the polygon uses 1 mil lines. So 10 1-mils lines would be needed to fill in a 10-mil wide area vs 1 10-mil line. And as you noticed, the file size is reduced, as well when wider lines are used for the polygon. I normally start with 16-mil polygons, but I use smaller widths if larger widths leave gaps between pads and vias.
Those hall effect sensors aren’t as good as the above, and they are move expensive (components for the above is around $5 in single quantity). Plus they take up a whole lot less room, and don’t need silly board “hacks”.
I get why you would use the Allegro hall effect sensors, the eagle package is already available. Although it would only take a few seconds to make a footprint for the LVK sense resistors.
I am the same guy you recommend it to thanks, however I can be a bit suborn and I have all the parts available to make this board, thus the only cost is the PCB, which is why I am trying to use it. If it fails I will just bridge the sensor out.
The capacitors used in the 5V circuit is also not optimal, tantalum capacitors would probably work better, but I have prototyped it with the electrolytics and it worked.
Edit: I am having a hard time sourcing the 1milliohm or two 0.5milliohm resistors in a Kelvin configuration. Know of any suppliers?
If you can’t find kelvin resistors, you can also use regular SMT ones and connect the sense lines to the inside of the pads. See section 2.4 in this document http://focus.ti.com/lit/ml/slua366/slua366.pdf for an example.
and I have all the parts available to make this board, thus the only cost is the PCB, which is why I am trying to use it. If it fails I will just bridge the sensor out.
