Hi
If I understand it correctly a 4 layer PCB with the setting (1+2*15+16) means that any manually added via
will “connect” to all the 4 layers ?
Let say that I dedicate layer 2 for GND and 15 for VCC and floodfilling these two layers with copper according
to the manual and then add a couple of vias manually (for thermal heatsinking) for a chip.
These via’s will also via connect to layer 2 and 15 (if they are placed “over” a floodfilled area ?
What should I do to avoid this, shall I add an area around the via’s that make the area 2 and 15 restricted
before floodfillign the layer 2 and 15 or is it other ways to do it ?
Sparcfun made a specific cam file, sfe-gerb274x.cam, for BatchPCB file generation.
Have SaprcFun also made a specific file for 4 layers as well or should I use Eagle’s own gerb274x-4layer.cam file ?
Regards Stefan