Hi,
My current project failed the DRC. 
The only orange highlighted things are component footprints. I am 80% sure that those are okay. A 6x6mm 28 pin QFN should not be pushing the boundaries. I know that I am missing something here. Can you someone help me out? I can email the eagle files to you. Thanks in advance.Unfortunately, your design violates our design rules of 8 mil traces with 8 mil trace spacing.
Top layer copper:
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In the past it has turned out that some PCB design programs will build up some bigger shapes with traces smaller than 7.8 mils. The DRC bot does not figure out that these pieces overlap to form a big piece that is plenty big enough.
Posts by SFEBPCB state that in such cases you should email support@batchpcb.com to ask that the design be approved manually.
I tweaked the layout to provide a lit bit bigger spacing for everything that was tight in my opinion. It still fails. I think it is the inductor footprint. I built the package with a SMD pad for the center and then polygons to make the weird ‘c’ shape. I emailed tech support.
The polygons are not connected to the net so are seen as shorting to the pads.
An error that you can ignore because you know that it is OK. 
Why would the batchPCB flag that? I thought something like that would be the ERC only.
This is your answer. Are you looking for something more?analogon:
In the past it has turned out that some PCB design programs will build up some bigger shapes with traces smaller than 7.8 mils. The DRC bot does not figure out that these pieces overlap to form a big piece that is plenty big enough.Posts by SFEBPCB state that in such cases you should email support@batchpcb.com to ask that the design be approved manually.
Nope. Tech support responded today. My board is ordered. I was just responding to mattylad’s comment this morning.
I’ll post pictures of the project when everything arrives in the mail.
Quick teaser:
8x 1Amp Buck LED driver.
uC
2x 10W RGBW LEDs
12 Feet of fiber optic
