BatchPCB:
Unfortunately, your design violates our design rules of 8 mil traces with 8 mil trace spacing.
I know I have a lot of minor things wrong with my board that I plan to fix later, but this error doesn’t seem to apply. All my wires are .01in and are proper spaced. I submitted ~6 versions tonight, moving things around etc, and they all failed.
Can someone take a look at my board file and tell me what I am doing wrong?
Di you check your e-mail attachment? Usually it has an image showing where the problem is.
I don’t see any problem with the board. You might want to specify an isolate value for your polygons.
What does the gerber image show? Myabe there’s just an gerber error, like the levels ar offset or something.
I think that SFE has a file you can use for DRC according to the Batch PCB rules. Have you tried using that?
Leon
Doh! I didn’t enter an isolation value for the polygon. That is probably it, I’ll try again tonight. Thanks.
Here are the image attachments. Nothing jumps out at me.
Red mark on the bottom right of the board. The hole outline is too close to your outside dimension.
Yes, that did the trick. Moving that spacer allowed DRC to pass. I also set that polygon isolation, because that is just good practice.
Thanks again everyone~!
