Hi,
Some time ago I began my project “etherled”. It was gone have 12 LEDs controlled via the network. I have finally completed the schematic and board and would like you to review it. Since this is my first board/schematic using an PIC24 and ENC28J60 I want to make sure everything is in order before I etch the PCB.
[Board](http://dl.getdropbox.com/u/1008610/etherled/etherled_brd.pdf)](http://dl.getdropbox.com/u/1008610/etherled/etherled_sch.pdf)
Post the Eagle files. That PDF of the board is too difficult to decipher and there are things on it that look too close together, but it’s impossible to tell due to the quality of the image and not know what the nets actually are.
[Eagle brd](http://dl.getdropbox.com/u/1008610/etherled/main.brd)](http://dl.getdropbox.com/u/1008610/etherled/main.sch)
Are you going to get this made up?
There’s one DRC error for clearance. The via that goes to the bottom ground below the PHY.
You should knock the 90 degree angles off of some of the traces. Other than some things that are strictly cosmetic it looks okay.
If you are getting it made up, you want to clean up all the labels and values on the soldermask.
There are some rules about running your traces from the PHY to the jack. TX and RX should be a certain distance apart; best to put a bit of ground between them. I can’t really remember the specifics, though.
Well, that’s the limit of my very amateurish help.
In no particular order:
a) Your power bus kinda snakes around the board. I’d beef that up a bit over its 16mil version, and try to do more direct paths to ICs (such as the Ethernet part!)
b) Double check your PHY wiring. This is critical - if there is a reference design available, follow it!
b1) One trace under the connector is a bit fishy and will likely cause DRCs (N$6)
c) Might as well give the VReg a VCC flood in which to heatsink too. You have the space.
d) Remember to emit a Milling layer in Gerbers or else your power jack will be very hard to solder onto the board :).
e) Add a bottom ground flood (see your ethernet PHY for more details, they can be picky)
When I have some time over I will make the modifications to the board. Thanks for the reviews.
I was thinking of etching the board myself. Since I’m a student it seems to expensive to just buy one manufactured pcb and in the process I learn something new.
If I only have one SPI chip I don’t need to use the “chip select” input do I?
I couldn't find anything about that in the ENC28J60 datasheet, so perhaps it's not that very important.There are some rules about running your traces from the PHY to the jack. TX and RX should be a certain distance apart; best to put a bit of ground between them. I can’t really remember the specifics, though.
If you search ‘ethernet traces pcb’ you’ll find some stuff. Everything I followed when making mine was from and appnote for the Wiznet device I used.
http://www.wiznet.co.kr/rg4_board/down. … &mode=down
CS is usually not optional and generally signals the start of a transmission when it’s pulled low.
I etch my own boards. I use standard toner transfer with Staples ‘photo paper’. It works well, but it can require some practice to get it working well.
I’ve redesigned the board a little.
I added a chip select line, a second ground plane and I rerouted the board. I also increased the width of the power lines to 24mil.
I was forced to use some vias to route the ethernet tx/rx signals. The wiznet guide line does not recommend doing so - but I couldn’t find any other way to route those signals. 
[Board v2](http://dl.getdropbox.com/u/1008610/etherled/v2/mainv2.brd)](http://dl.getdropbox.com/u/1008610/etherled/v2/mainv2.sch)
Looks good. I’ll just be slightly pedantic now, because I can be.
Decoupling caps (C12, C16, etc) should have the power bus coming first to the cap, and then to the IC power pin. For instance, C13 = ok.
You can tie the top and bottom ground planes together in many more places, especially near decoupling caps. Add a GND via near the pad of each one. If you are hand etching, its a moot point due to the difficulty of making your own plated holes.
I see you upped the regulator package size. I haven’t computed power requirements, but do you need it?
You have annular rings on your mounting holes. No real reason as far as I can tell :).
Small DFM thing for hand building: If you can place components at 90 degree angles between pads, you will inevitably do that. For example, R4/R5/C5. Even if the silk screen is screaming “put them this way” 
If you do get the board built professionally, you have a lot of overlapping silkscreen. Use the SMASH tool, and move the identifiers to sane locations.
I’m slightly pedantic myself. I spent more time then I should to try to route the ethernet tx/rx signals without vias, only to release that it wasn’t possible. 
Life would be easier if one could make own plated thru-holes easy and cheap.
I’m etching the board myself so placing to many vias is a no no. I’ve didn’t clean up the silkscreen in case that the board routing was a disaster. Should it have been bad I wouldn’t need to rearrange the silkscreen again.
Tomorrow I will see what I can do about the power bus and the caps.
[Hackaday had an article about the pic24 and enc28j60, so I used their design as a templet. They use this regulator package size. Also they mention that the enc28j60 is very power hungry.
As for the annular rings on the mounting holes I have no idea how to get ride of them.
I'm not quite sure what you mean.](http://hackaday.com/2008/09/25/web-server-on-a-business-card-part-2/")Small DFM thing for hand building: If you can place components at 90 degree angles between pads, you will inevitably do that. For example, R4/R5/C5. Even if the silk screen is screaming “put them this way”
I’ve rerouted the power bus so that it reaches the caps first. Also the DRC gives my some odd error about drill size for the vias.
[Board 2.1](http://dl.getdropbox.com/u/1008610/etherled/v2.1/mainv2.1.brd)](http://dl.getdropbox.com/u/1008610/etherled/v2.1/mainv2.1.sch)
To get rid of angular rings, use the hole tool in the board editor, not the via tool.
I modified the board a bit further and added a header for power off button connection. Can someone take a quick look at the board/schematic? I want to believe it’s finished now, if so I’m gone etch tomorrow :D.
Thank you all for the help. Without your help my first pcb would go right down to the trash bin.](http://dl.getdropbox.com/u/1008610/etherled/v2.2/mainv2.2.brd)](http://dl.getdropbox.com/u/1008610/etherled/v2.2/mainv2.2.sch)
Bottom left. You have a trace going around R10 that looks pretty close.
Top right. I assume C11 is a decoupling cap. You need to put it ‘inline’ with the power path to the chip, rather than off on a dead end trace.
I’m guessing JP5 is a switch or something.
JP4 is all ground connections?
Your etching this yourself? You might as well increase all of the trace widths. You have the room for it.
Otherwise, it looks fine to me. I also have my TX and RX lines going through a via.
I was thinking of connection JP5 to a power switch. JP4 is meant to provide ground for the LEDs that are gone be connected to the PIC24 outputs. I reduced the JP4 pin count to two.
Is there an easy way to increase the width of all traces in eagle?](http://dl.getdropbox.com/u/1008610/etherled/v2.3/mainv2.3.brd)](http://dl.getdropbox.com/u/1008610/etherled/v2.3/mainv2.3.sch)
Select change → width, then group them and select them.
It’s not that big, I tend to just select change → width then click around like a maniac.
