Hi,
I have NXP i.MX8 EVB. The chip include two ARM M4 and Quad Core ARM A35. CoreSight CPU debug registers for M4 and A35 are placed DAP AP, each with different AP. According to NXP document the Quad Core A35 should be on AP 4.
The automatic DAP scan didn’t find A35 CPU debug registers at all. See log below.
I seems there is no ROM table on AP 4 or some other issue.
I specify DAP AP number to 4 as follow:
jtag newtap MyTAP_NXP cpu -irlen 4 -expected-id 0x1890201d -enable
dap create MyDAP_NXP.dap -chain-position MyTAP_NXP.cpu -ignore-syspwrupack
cti create MyCTI_NXP -dap MyDAP_NXP.dap -ap-num 4 -ctibase 0x80420000
target create MyTarget_NXP aarch64 -dap MyDAP_NXP.dap -ap-num 4
From NXP:
AP Index 4: APB-AP, ROM Table base address 0x80000000
CSTFunnel: base address 0x80020000; ID: 0x00000908
CSTPIU: base address 0x80030000; ID: 0x00000912
CSTMC: base address 0x80040000; ID: 0x00000961
CSATBReplicator: ase address 0x80050000; ID: 0x00000909
CSGPR: base address 0x80070000; ID 0x000009A4
CSCTI: base address 0x80090000; ID 0x00000906
Cortex-A35: base address 0x80410000; ID 0x00000D03
CSTFunnel: base address 0x00000000; ID ???
CSCTI: base address 0x80420000; ID 0x000009A8
CSPMU: base address 0x80430000; ID 0x000009D3
CSETM: base address 0x80440000; ID 0x0000095D
Cortex-A35: base address 0x80510000; ID 0x00000D03
CSCTI: base address 0x80520000; ID 0x000009A8
CSPMU: base address 0x80530000; ID 0x000009D3
CSETM: base address 0x80540000; ID 0x0000095D
Cortex-A35: base address 0x80610000; ID 0x00000D03
CSCTI: base address 0x80620000; ID 0x000009A8
CSPMU: base address 0x80630000; ID 0x000009D3
CSETM: base address 0x80640000; ID 0x0000095D
Cortex-A35: base address 0x80710000; ID 0x00000D03
CSCTI: base address 0x80720000; ID 0x000009A8
CSPMU: base address 0x80730000; ID 0x000009D3
CSETM: base address 0x80740000; ID 0x0000095D
Is there a way manually specify CPU debug registers base address on DAP AP bus ? (as -ctibase)
Assuming ROM table is missing or incorrect and auto-detect is not working.
How to specify which of the CPU in MyTAP_NXP (there are x4) is been use when issue MyTAP_NXP mdw ?
If there was an option to specify CPU debug registers base address I could select the CPU.
Is there a command that scan all AP in the DAPs (APSEL 0x00 to 0xFF) ?
I manually use ‘dap info’ command from value of 0 until it stop working. As I know APSEL is 8 bit so there may be up to 256 AP on the DAP.
Alos note that ‘dap info’ command to un-implemented AP stop the script, why is that ?
Thanks.
GNU MCU Eclipse 64-bit Open On-Chip Debugger 0.10.0+dev-00462-gdd1d90111 (2019-01-18-11:42)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
.
GDB Configuration
breakpoint type is not overridden
.
Interface Configuration.
Important: J-Link must use the WinUSB driver and not SEGGER driver.
adapter speed: 1000 kHz
init …
Info : J-Link V9 compiled Apr 20 2018 16:47:26
Info : Hardware version: 9.20
Info : VTarget = 1.790 V
Info : clock speed 1000 kHz
Info : JTAG tap: MyTAP_NXP.cpu tap/device found: 0x1890201d (mfg: 0x00e (Freescale (Motorola)), part: 0x8902, ver: 0x1)
Error: JTAG-DP STICKY ERROR
Error: Could not initialize the APB-AP
Info : gdb port disabled
.
dap Info …
AP 0:
AP ID register 0x44770004
Type is MEM-AP AXI
MEM-AP BASE 0x00000002
No ROM table present
AP 1:
AP ID register 0x24770011
Type is MEM-AP AHB
MEM-AP BASE 0xe00ff003
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x04000bb4c4
Designer is 0x4bb, ARM Ltd.
Part is 0x4c4, Cortex-M4 ROM (ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
ROMTABLE[0x0] = 0xfff0f003
Component base address 0xe000e000
Peripheral ID 0x04000bb00c
Designer is 0x4bb, ARM Ltd.
Part is 0xc, Cortex-M4 SCS (System Control Space)
Component class is 0xe, Generic IP component
ROMTABLE[0x4] = 0xfff02003
Component base address 0xe0001000
Invalid CID 0x00000000
ROMTABLE[0x8] = 0xfff03003
Component base address 0xe0002000
Peripheral ID 0x04002bb003
Designer is 0x4bb, ARM Ltd.
Part is 0x3, Cortex-M3 FPB (Flash Patch and Breakpoint)
Component class is 0xe, Generic IP component
ROMTABLE[0xc] = 0xfff01003
Component base address 0xe0000000
Invalid CID 0xb1b1b1b1
ROMTABLE[0x10] = 0xfff41002
Component not present
ROMTABLE[0x14] = 0xfff42003
Component base address 0xe0041000
Peripheral ID 0x04000bb925
Designer is 0x4bb, ARM Ltd.
Part is 0x925, Cortex-M4 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
ROMTABLE[0x18] = 0xfff43002
Component not present
ROMTABLE[0x1c] = 0xfff44003
Component base address 0xe0043000
Peripheral ID 0x04001bb908
Designer is 0x4bb, ARM Ltd.
Part is 0x908, CoreSight CSTF (Trace Funnel)
Component class is 0x9, CoreSight component
Type is 0x12, Trace Link, Funnel, router
ROMTABLE[0x20] = 0x0
End of ROM table
AP 2:
AP ID register 0x24770011
Type is MEM-AP AHB
MEM-AP BASE 0xe00ff003
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x04000bb4c4
Designer is 0x4bb, ARM Ltd.
Part is 0x4c4, Cortex-M4 ROM (ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
ROMTABLE[0x0] = 0xfff0f003
Component base address 0xe000e000
Peripheral ID 0x04000bb00c
Designer is 0x4bb, ARM Ltd.
Part is 0xc, Cortex-M4 SCS (System Control Space)
Component class is 0xe, Generic IP component
ROMTABLE[0x4] = 0xfff02003
Component base address 0xe0001000
Invalid CID 0x00000000
ROMTABLE[0x8] = 0xfff03003
Component base address 0xe0002000
Peripheral ID 0x04002bb003
Designer is 0x4bb, ARM Ltd.
Part is 0x3, Cortex-M3 FPB (Flash Patch and Breakpoint)
Component class is 0xe, Generic IP component
ROMTABLE[0xc] = 0xfff01003
Component base address 0xe0000000
Invalid CID 0xb1b1b1b1
ROMTABLE[0x10] = 0xfff41002
Component not present
ROMTABLE[0x14] = 0xfff42003
Component base address 0xe0041000
Peripheral ID 0x04000bb925
Designer is 0x4bb, ARM Ltd.
Part is 0x925, Cortex-M4 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
ROMTABLE[0x18] = 0xfff43002
Component not present
ROMTABLE[0x1c] = 0xfff44003
Component base address 0xe0043000
Peripheral ID 0x04001bb908
Designer is 0x4bb, ARM Ltd.
Part is 0x908, CoreSight CSTF (Trace Funnel)
Component class is 0x9, CoreSight component
Type is 0x12, Trace Link, Funnel, router
ROMTABLE[0x20] = 0x0
End of ROM table
AP 3:
AP ID register 0x84770001
Type is MEM-AP AHB
MEM-AP BASE 0x00000002
No ROM table present
AP 4: ???
AP ID register 0x54770002
Type is MEM-AP APB
MEM-AP BASE 0x00000002
No ROM table present
AP 5:
AP ID register 0x84770001
Type is MEM-AP AHB
MEM-AP BASE 0x00000002
No ROM table present
AP 6:
AP ID register 0x84770001
Type is MEM-AP AHB
MEM-AP BASE 0x00000002
No ROM table present