DRC Error - Trace too narrow

Archive BatchPCB
1

Hi,

Using Sparkfun’s drc file, Eagle does not detect any violation when I proceed with a DRC.

However, BatchPCB robot fails my board. Here is the log I get:

unmatched 274X paramblock OFA0B0 - len 6
Macro Name = OC8
Macro Consuming 5,1,8,0,0,1.08239X$1,22.5 [2]
PUSH 1.000000
PUSH 8.000000
PUSH 0.000000
PUSH 0.000000
PUSH 1.082390
FETCH 1
MUL
PUSH 22.500000
PRIM 5
Parse_OK
Arg: 0.0640
Looking up macro OC8 [0x1b96160]
Beginning GCODE run
Ending GCODE run
Created 1689 polygons
Found 0 errors
Partitioning....
Grouping...
Distance testing
MergeCount: 1473
tests: 159755
Board boundaries: Rect: [0.327400,0.335100] -> [2.903600,2.985100], w: 2.576200, h: 2.650000
Found 216 groups
lengthdb size 0
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow
DRC Error - trace to narrow

How to identify which trace is too narrow? I have no idea where traces are too narrow, the minimum width I use for traces is 11 mils!

Thanks,

Jean

2

You don’t get a nice little image with the issue area in orange?

I got my first error, because I failed to change some text I had on the copper layer to Vector and it gave an image with the effected area’s in orange.

3

TheDirty:
You don’t get a nice little image with the issue area in orange?

I got my first error, because I failed to change some text I had on the copper layer to Vector and it gave an image with the effected area’s in orange.

Yes, I reviewed the drawing and the outline was in orange. The issue was that the outline (dimensions) had a width greater than 0. This is what triggered the error. I set the outline to a width of 0 and that fixed the issue.

Thanks!

4

I’m having the same problem, but I’m using FreePCB, and as far as I can tell, there’s no way to set the width of the board outline. I tried removing the board outline, but it won’t let me generate the Gerber files without it. I tried editing the Gerber files with a text editor, but I can’t figure out what to change.

This seems to be a bug in the DRC, but I can’t get my board made until I get past it.

5

use the change command. select width, 8 mil (or .008) and click on the outline. resubmit the job.

by the way, what cam file are you using?

6

I’m having the same problem, but I’m using FreePCB, and as far as I can tell, there’s no way to set the width of the board outline.

Its a hack, but I did this by running the FreePCB CAM twice. First time, disable the board outline and run for all layers. Second time, enable the board outline but disable all layers but top/bottom silkscreen. (It will overwrite the old silkscreen layers.) The result should be a file set with the outlines on just the silkscreen layers which will allow it to pass the SFE DRC.

Disclaimer: While this allowed me to pass the DRC, I have not actually had a board manufactured using FreePCB (normally use Eagle).

7

In regards to the problem with FreePCB, you can change the board width in the “Generate Gerber and Drill Files” dialog box that comes up whenever you want to generate the CAM files.