I’ve imported some artwork into my board via the import-bmp.ulp in Eagle and it looks great. If I place the artwork in the top copper layer, I get DRC trace width errors. Also, the Advanced Circuits FreeDFM also complains about the copper logo. Is there a way to fix this?
Should I just get the board to pass DRC and FreeDFM before I add the copper artwork and then ignore the new art-related errors?
If DRC and FreeDFM complains when the artwork is in place, the boardhouse will most likely complain as well if you send off the gerbers for production. Only way to fix it, as far as I know, is to make the width of the tracks wider. Could also be that it complains about clearance between the tracks as well.
So how do I make the tracks wider? None of the things I tried seemed to help. Advanced Circuits called me back after the FreeDFM and said none of the errors would make a difference in manufacturing, but I’d still like to figure out a way to generate error-free gerbers with logos and images. The letters in the text are too close together so I get clearance complaints as well as narrow trace errors.
StigOE:
If DRC and FreeDFM complains when the artwork is in place, the boardhouse will most likely complain as well if you send off the gerbers for production. Only way to fix it, as far as I know, is to make the width of the tracks wider. Could also be that it complains about clearance between the tracks as well.
ScottH:
So how do I make the tracks wider? None of the things I tried seemed to help. Advanced Circuits called me back after the FreeDFM and said none of the errors would make a difference in manufacturing, but I’d still like to figure out a way to generate error-free gerbers with logos and images. The letters in the text are too close together so I get clearance complaints as well as narrow trace errors.
If they said the error wouldn't be a problem, I don't think I would have bothered to do anything about the logo.
I’ve tried changing the trace width, but it appears that the import-bmp.ulp program builds the graphics out of some other primitive (rectangles???) so that didn’t work. The net name idea is a good one. I’ll have to give that a shot.
For this board, I can just do the FreeDFM and DRC check before I slap the logo on as a final step, but it would be nice if I could make changes to the board while the graphics were there. This would be more important for more complicated designs. Besides, removing the graphics to do the DRC check is a pain.
I guess I need to delve into import-bmp.ulp and see how it really works.
Thanks,
-Scott
StigOE:
ScottH:
So how do I make the tracks wider? None of the things I tried seemed to help. Advanced Circuits called me back after the FreeDFM and said none of the errors would make a difference in manufacturing, but I’d still like to figure out a way to generate error-free gerbers with logos and images. The letters in the text are too close together so I get clearance complaints as well as narrow trace errors.
If they said the error wouldn't be a problem, I don't think I would have bothered to do anything about the logo.